1. Technical Field
The present invention relates, generally, to the packaging of semiconductor chips and, more particularly, to wire bond techniques effective in reducing parasitic inductance in microelectronic components, i.e. packaged semiconductor chips.
2. Background Information
Recent advances in the design and fabrication of semiconductor devices has dramatically increased their speed and density but has, at the same time, led to significant challenges in the field of semiconductor packaging. These challenges are particularly acute with respect to minimizing the parasitic resistance, inductance, and capacitance (RLC) effects introduced by the various interconnect elements e.g., the leads, paddles and bond wires.
More particularly, in power integrated circuits (ICs) such as voltage regulators and the like, parasitic effects can be performance-limiting factors. During turn-off of a switching device, leakage currents flow in the parasitic loop formed by the capacitance of the switching device with the bulk capacitors at the input. The package parasitic inductance in this loop sets up an oscillation, causing ringing-voltage across the switching device. The overshoot amplitude of the ringing voltage is directly proportional to the total package parasitic inductance of the loop and the current turn-off rate. If the loop inductance is sufficiently high, the overshoot amplitude may reach dangerously high levels and permanently damage the switching device itself.
Moreover, as package parasitics increase, device efficiency decreases. This drives higher power dissipation in the device, forcing it to operate at higher temperatures and leading to early device failure. Therefore, there is a need in the microelectronic component art to achieve a low parasitic package to improve device efficiency.
The total loop inductance in a current path is the sum of the partial self-inductances of each element in that path and the mutual inductances between them. For two inductors in series, for example, the total inductance L is given by:L=L1+L2±2Mwhere L1 and L2 are the partial self-inductances of the individual inductors and M is the mutual inductance between them. For n wires, total parasitic inductance is n times L plus or minus n times M.
The sign of M will depend on the direction of current flow in the inductors; that is, current flow in the same direction results in a positive M, and current flow in the opposite direction results in a negative M. Thus, when the inward and outward current paths in a current loop are brought closer to each other, the negative mutual inductance between them increases and the overall loop inductance reduces. However, existing microelectronic components have not provided a substantial negative mutual inductance.
For example, FIG. 1 shows a circuit schematic of a typical DC voltage regulator IC 102 which includes a P-type power MOSFET (PFET die 104) and one or more N-type power MOSFETs (nFET dice 106) in the buck-regulator configuration. All these dice 104 and 106 may exist in individual integrated circuit (IC) packages or may be co-packaged together in a multi-chip package as a single component. When high-side pFET switch 104 is turned off by, for example, a pulse width modulation (PWM) control input at its gate, the off-state high voltage that appears across PFET 104 sets up a leakage current in loop 114 as shown. In case of co-packaged dice in a multi-chip package, the total inductance of loop 114 is predominantly made up of package parasitic inductances 108(L1), 112(L2), and 110(L3), and the equivalent series inductance (ESL) of the input capacitors 116 and the mutual inductances between them. At the package level housing for example pFET 104), it is then important to reduce the partial self-inductance values of 108(L1), and 112(L2), and/or increase the mutual coupling between the wires that carry current in opposite directions. The first of the two wires carries the Vcc current and contains parasitic inductor 108 and has a resistance of R1. The second wire carries the Vsw current and contains parasitic inductor 112 and has a resistance of R2. The third wire connects nFET 106 to ground and contains parasitic inductor 110 and resistance R3. In case of individually packaged dice 104 and 106, the inductances 108, 112 and 110 and resistances R1, R2 and R3 will be significantly higher that their multi-chip package values due to significant contributions from board level interconnect that provide electrical connections between these devices. The output of the buck converter 102 is provided to the load via output inductor 118 and capacitor 120.
FIG. 2 shows a typical prior art Quad Flat no-Lead (QFN) lead frame used in conjunction with a DC regulator IC such as the one discussed above. The input Vcc to PFET die 201 is through a set of bond wires 202, and the Vsw current exiting pFET die 201 is carried through a second set of bond wires 203 that are down-bonded to Vsw paddle 204. General logic bond wires 205 are typically brought out at the ends of the die, and their respective bond pads 206 are located near the edges of the die, on all sides, to reduce wire length.
Prior art packages such as the one illustrated in FIG. 2 become increasingly unsatisfactory in a number of respects, especially as switching speed increases. In high switching speed applications, for example, the inductance of the wires becomes prohibitively high, causing ringing. While this ringing effect can be minimized by shortening the bond wires and/or adding additional wires in parallel, a point of diminishing returns is quickly reached. This is due to the lower bound on the mutual inductive coupling that could be achieved between the forward and return current paths that is dictated by the spatial separation of the respective bond pads and bond wires for those currents.
The aforementioned wire bond configuration is also unsatisfactory in that the wire bond pads 206 are typically positioned near the outside edges of the die. This provides the shortest wire lengths, but still adds substantial RLC parasitics to the overall circuit due to the need for the current to travel laterally across the die surface. Additional bond pads 206 could be placed in the inner regions of the die surface to alleviate this latter problem, but then the increased wire length will result in increased inductance.
Another prior art method used to reduce inductance is to utilize flip-chip interconnects instead of wire bonds. While this interconnect method can improve performance, it also significantly increases the packaging costs.
The aforementioned failings of the prior art have remained unresolved in a multi-chip package, i.e. a package that houses more than one chip. Achieving loop inductance reduction may hit a roadblock, particularly in low cost wire-bonded lead frame multi-chip packages. The wire bonding process requires that there be a sufficient spatial separation between the individual chips, thus setting a lower bound on the loop inductance reduction that can be achieved by known techniques.
Methods and structures are therefore needed in order to overcome these and other limitations of the prior art.